Renesas Electronics /R7FA6E2BB /CANFD_B /CFDGCFG

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Interpret as CFDGCFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TPRI 0 (0)DCE 0 (0)DRE 0 (0)MME 0 (0)DCS 0 (0)CMPOC 0TSP0 (0)TSSS 0ITRCP

DCS=0, MME=0, DCE=0, TSSS=0, CMPOC=0, DRE=0, TPRI=0

Description

Global Configuration Register

Fields

TPRI

Transmission Priority

0 (0): ID priority

1 (1): Message buffer number priority

DCE

DLC Check Enable

0 (0): DLC check disabled

1 (1): DLC check enabled

DRE

DLC Replacement Enable

0 (0): DLC replacement disabled

1 (1): DLC replacement enabled

MME

Mirror Mode Enable

0 (0): Mirror mode disabled

1 (1): Mirror mode enabled

DCS

Data Link Controller Clock Select

0 (0): Internal clean clock

1 (1): External clock source connected to CANMCLK pin

CMPOC

CANFD Message Payload Overflow Configuration

0 (0): Message is rejected

1 (1): Message payload is cut to fit to configured message size

TSP

Timestamp Prescaler

TSSS

Timestamp Source Select

0 (0): Source clock for timestamp counter is peripheral clock

1 (1): Source clock for timestamp counter is bit time clock

ITRCP

Interval Timer Reference Clock Prescaler

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